uvm Jobs

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Onsite Mid-level Verification Engineer, UVM, SystemVerilogJob Title - Onsite Mid-level Verification Engineer, UVM, SystemVerilog

Intelliswift Software IncCompany Name - Intelliswift Software Inc

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Newark, California, USA

Contract

Mid-level Verification Engineer with 5-8 years of experience of pure verification in FPGA. This is a pure Verification Engineer role. This position is onsite in the greater San Jose Bay Area. What you will be doing: Purely verification of FPGAProgramming using SystemVerilogDevelop OO testbench infrastructureDevelop test cases using UVMScripting What you will need: 5-8 years in pure VerificationSolid in SystemVerilog programmingExperience with UVM, Universal Verification MethodologyExperience

Senior Principal Engineer, Verification (Ethernet, Serdes, UVM)Job Title - Senior Principal Engineer, Verification (Ethernet, Serdes, UVM)

Marvell Semiconductor Inc.Company Name - Marvell Semiconductor Inc.

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Santa Clara, California, USA

Full-time

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and be

Design Verification EngineerJob Title - Design Verification Engineer

Avance ConsultingCompany Name - Avance Consulting

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Remote

Full-time

<>Key Responsibilities:Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely with RTL designers to resolve issuesExecute regressio

Design Verification EngineerJob Title - Design Verification Engineer

Mirafra IncCompany Name - Mirafra Inc

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San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

Verification Engineer IVJob Title - Verification Engineer IV

SPECTRAFORCE TECHNOLOGIES Inc.Company Name - SPECTRAFORCE TECHNOLOGIES Inc.

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Sunnyvale, California, USA

Contract

Verification Engineer IV Sunnyvale CA (Hybrid) 6 months (Possible extension) Job Description Summary: The main function of the Verification Engineer is to work with a group of researchers and engineers to own the electrical system level verification of Client's products. Working closely with researchers, architects, and designers in architecting methods of electrical verification for multiple state of the art systems. Using verification skills to define verification requirements, create test ca

ASIC Design Verification EngineerJob Title - ASIC Design Verification Engineer

TranSquared incCompany Name - TranSquared inc

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San Jose, California, USA

Contract

Job Title:- ASIC Design Verification Engineer Duration:-12 months+ Location:-San Jose , CA(Onsite - Work from Office 5 days per week). About the Role: We are seeking a highly skilled and motivated ASIC Design Verification Engineer with over 6 years of experience in the field of verification. As an Individual Contributor, he/she will play a crucial role in ensuring the quality and reliability of our cutting-edge ASIC designs, contributing to industry-leading innovations. Key Responsibilities: Dev

Design Verification EngineerJob Title - Design Verification Engineer

Innova Solutions, IncCompany Name - Innova Solutions, Inc

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Remote or Mountain View, California, USA

Third Party, Contract

A client of Innova Solutions is looking for an Design Verification Engineer. Position type: Contract Duration: 12+ Months Location: Mountain View, CA (Onsite Job) As a Design Verification Engineer, you will need: Minimum Qualifications: Experience in SV and UVM and good debugging skills.Understanding of AMBA protocols.Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/co

Senior Design Verification Engineer-12+Yrs Candidate neededJob Title - Senior Design Verification Engineer-12+Yrs Candidate needed

SivaltechCompany Name - Sivaltech

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San Diego, California, USA

Contract, Third Party

Job Title: Senior Design Verification Engineer Company: Sivaltech Location: San Diego, CA Job Type: Full-time About Sivaltech: Sivaltech is a leading technology company driving innovation and excellence in the industry. We're seeking an experienced Senior Design Verification Engineer to join our team in San Diego, CA. Job Description: As a Senior Design Verification Engineer, you'll develop and execute verification plans for complex digital designs, working closely with cross-functional teams to

System IP Design Verification EngineerJob Title - System IP Design Verification Engineer

BayOne SolutionsCompany Name - BayOne Solutions

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Austin, Texas, USA

Contract

Title: Senior System IP Design Verification Engineer (Contract)Duration: Through 09/12/2025Pay: $90/hr $120/hr Job OverviewWe're looking for a Senior Staff System IP Design Verification Engineer to lead verification efforts for advanced System IP (coherent interconnects, caches). This is a hands-on role requiring deep experience in UVM, SystemVerilog, and gate-level simulation (GLS). Key ResponsibilitiesDevelop reusable testbenches and verification environments from scratch Drive best practices

Verification EngineerJob Title - Verification Engineer

Procal TechnologiesCompany Name - Procal Technologies

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Warren, New Jersey, USA

Contract

Job Title: Junior Verification Engineer Location: New Jersey Duration: 12+ Months Job Description As a Junior UVM SystemVerilog Verification Engineer, you will be responsible for assisting in the development and execution of test plans using Universal Verification Methodology (UVM) to validate the functionality, performance, and reliability of FPGA designs. You will work closely with senior engineers to gain hands-on experience in digital design verification. Key Responsibilities: Assist in deve

Mixed-Signal Design Verification EngineerJob Title - Mixed-Signal Design Verification Engineer

Talent Junction, LLC.Company Name - Talent Junction, LLC.

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San Jose, California, USA

Contract, Third Party

Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key Technical Skills:UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc. Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters

Verification Engineer role in Bay Area, CA/Austin, TX (Onsite)Job Title - Verification Engineer role in Bay Area, CA/Austin, TX (Onsite)

Yochana IT SolutionsCompany Name - Yochana IT Solutions

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San Francisco, California, USA

Third Party, Contract

Should be good in hands-on using SV/UVM. AMBA (especially AXI is a must) Experience in updating sequence, test, running and debugging Experience in PCIE or C based is a plus

Design Verification EngineerJob Title - Design Verification Engineer

SivaltechCompany Name - Sivaltech

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Santa Clara, California, USA

Contract, Third Party

Job Title: Design Verification Engineer (DV) Company: Sivaltech Location: Santa Clara, CA Job Type: Full-time About Sivaltech: Sivaltech is a leading technology company driving innovation in the industry. We're seeking an experienced Design Verification Engineer to join our team in Santa Clara, CA. Job Description: As a Design Verification Engineer, you'll develop and execute verification plans for complex digital designs, focusing on Ethernet PHY or PCS. You'll work closely with cross-functiona

SOC Verification Engineer- Remote- USAJob Title - SOC Verification Engineer- Remote- USA

Yochana IT SolutionsCompany Name - Yochana IT Solutions

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Contract, Third Party

8+ years experience Strong in SV / UVM and full chip verification Networking protocol knowledge PCIe, Ethernet, CXL etc. Testbench creation & Scoreboarding

Design Verification Engineer || Mountain View, CA (Onsite)Job Title - Design Verification Engineer || Mountain View, CA (Onsite)

E-Solutions, Inc.Company Name - E-Solutions, Inc.

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Mountain View, California, USA

Full-time

Job Role- Design Verification Engineer Location- Mountain View, CA (Onsite) Job Descriptions- Key Responsibilities: Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage analysis, and close functional/code cover

Design Verification EngineerJob Title - Design Verification Engineer

Mindsource IncCompany Name - Mindsource Inc

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Sunnyvale, California, USA

Contract

Title: Sr. Design Verification Engineer Location: Onsite - Sunnyvale, CA (or) Austin, TX Duration: Long-term Type: Contract (W2/C2C) Rate: $110-$115/hr Responsibilities: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause, and resol

Junior Verification EngineerJob Title - Junior Verification Engineer

GlobalLogic Inc.Company Name - GlobalLogic Inc.

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Warren, New Jersey, USA

Third Party, Contract

Job Description: Assist in developing and implementing UVM-based verification plans for FPGA designs.Perform functional and regression testing for digital hardware components.Develop and maintain test benches, test cases, and automation scripts in System Verilog.Analyze test results, debug issues, and collaborate with senior engineers to resolve defects.Ensure compliance with industry standards and customer requirements.Document test procedures, results, and defect tracking.Continuously learn an

Design Verification EngineerJob Title - Design Verification Engineer

LeadStack, Inc.Company Name - LeadStack, Inc.

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No location provided

Full-time, Contract

Lead Stack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world. TITLE: Design Verification Engineer LOCATION: San Jose CA/ Austin TX DURATION: 5+ Months with possible extension Rate: $90-$110/hr on W2 Job Descriptio

Design Verification EngineerJob Title - Design Verification Engineer

BayOne SolutionsCompany Name - BayOne Solutions

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Austin, Texas, USA

Contract

Title - System IP Design Verification Engineer Duration 6+ Months Job ID - 429704 Location - 3900 N Capital of Texas Hwy, Austin, TX, USA OR 3655 N 1st St, San Jose, CA, USA Job Description As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification

Design Verification Engineer at Santa Clara, CA (Hybrid)Job Title - Design Verification Engineer at Santa Clara, CA (Hybrid)

Infobahn Softworld Inc.Company Name - Infobahn Softworld Inc.

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Santa Clara, California, USA

Contract, Third Party

Role Title: Design Verification Engineer Location: Santa Clara, CA, 95054 (Hybrid 3 days a week) Duration: 12+ months contract Job Duties: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the