uvm Jobs

1 - 20 of 138 Jobs

Senior UVM Digital Verification EngineerJob Title - Senior UVM Digital Verification Engineer

DraperCompany Name - Draper

•

Boston, Massachusetts, USA

Full-time

Job Description Summary: Draper's Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications. Job Description: Duties/Responsibilities Performs analysis approaches for a particular probl

System Verilog UVM Design Verification Test EngineerJob Title - System Verilog UVM Design Verification Test Engineer

U.S. Tech Solutions Inc.Company Name - U.S. Tech Solutions Inc.

•

Remote

Contract

Job Description: The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to drive the internal components and send data. Responsibilities: UVM/python test development for driving VIPs and other stimulus driversGeneration of test components such as monitors, scoreboards and python modelsCoverage closure and GLS bringup and testing Experience: 6+ years of experience with verification methodologies

UVM Digital Verification EngineerJob Title - UVM Digital Verification Engineer

DraperCompany Name - Draper

•

Remote or Cambridge, Massachusetts, USA

Full-time

Overview: Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas

FPGA UVM Design EngineerJob Title - FPGA UVM Design Engineer

Viasat, Inc.Company Name - Viasat, Inc.

•

Marlborough, Massachusetts, USA

Full-time

About us One team. Global challenges. Infinite opportunities. At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We're looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team. What you'll do Viasat is a rapidly growing technology company that crafts,

Principal UVM Digital Verification EngineerJob Title - Principal UVM Digital Verification Engineer

DraperCompany Name - Draper

•

Cambridge, Massachusetts, USA

Full-time

Senior UVM Digital Verification EngineerJob Title - Senior UVM Digital Verification Engineer

DraperCompany Name - Draper

•

Cambridge, Massachusetts, USA

Full-time

Design Verification EngineerJob Title - Design Verification Engineer

Innova Solutions, IncCompany Name - Innova Solutions, Inc

•

Mountain View, California, USA

Contract

A client of Innova Solutions is immediately hiring for a Design Verification Engineer Position type: Contract Location: Mountain View, CA-Onsite As a Design Verification Engineer, you will be responsible for: Job description: Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirements.Build UVM/System Verilog-based verification environments for IP/subsystem/SoC leve

Design Verification Engineer - SOCJob Title - Design Verification Engineer - SOC

Millennium Software, Inc.Company Name - Millennium Software, Inc.

•

San Jose, California, USA

Contract

Millennium Software & Staffing is looking for Design Verification Engineer SOC at San Jose, CA Below are the details: Title : Design Verification Engineer SOC Location : San Jose, CA TOP SKILLS: SOCUVM, System VerilogIntegrate GPU, CPU, Arm Based SystemPCIe, DDR, Ethernet, Bus ProtocolsPython Scripting Candidate should have average or above average Python SkillsExperience: 8+ years of experience in SOC, SystemVerilog/UVM methodologyExperience in EDA tools and scripting (Python, TCL, Perl, Shell

Design Verification Engineer RISC-V CPU DevelopmentJob Title - Design Verification Engineer RISC-V CPU Development

Xpeerant IncorporatedCompany Name - Xpeerant Incorporated

•

Portland, Oregon, USA

Full-time

Design Verification Engineer RISC-V CPU Development Are you passionate about cutting-edge CPU architecture and ready to take your verification skills to the next level? We re partnering with a global leader in RISC-V processor design to find talented Design Verification Engineers to join their high-impact VLSI team. You ll work alongside seasoned architects and engineers to verify next-generation RISC-V CPU cores, develop test benches from the ground up, and help shape the future of custom CPU I

Quantum Verification EngineerJob Title - Quantum Verification Engineer

Infinite Computer Solutions (ICS)Company Name - Infinite Computer Solutions (ICS)

•

Rochester, Minnesota, USA

Contract

Job Title: Quantum Verification Engineer Duration: 12+ Months (Possibility of Extension) Location: Rochester, MN (Onsite) Role & Responsibilities Verification Ownership: Take charge of the verification triage for microprocessor components, contributing to the identification of functional and performance issues pre-silicon production. Implement best practices and innovative methodologies to ensure robust and efficient verification processes.Documentation and Communication: Thoroughly document ver

Hardware Design EngineerJob Title - Hardware Design Engineer

Talent Software Services, IncCompany Name - Talent Software Services, Inc

•

Redmond, Washington, USA

Contract

Hardware Design Engineer 5Job Summary: Talent Software Services is in search of a Hardware Design Engineer for a contract position in Redmond, WA. The opportunity will be six months with a strong chance for a long-term extension.Primary Responsibilities/Accountabilities: Purpose of the Team: The team focuses on designing verifications for OVL programs (OVL1 and OVL3) and various designs in host networking groups. Key projects: Verification designs and writing test bench code. Performance will be

Design Verification EngineerJob Title - Design Verification Engineer

Mirafra IncCompany Name - Mirafra Inc

•

San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

Digital SoC Design Verification Principal Engineer/ManagerJob Title - Digital SoC Design Verification Principal Engineer/Manager

Island StaffingCompany Name - Island Staffing

•

San Jose, California, USA

Full-time

Digital SoC Design Verification Principal Engineer/Manager 140-225K (+ Pre-IPO Stock Options) San Jose, CA (hybrid 1 day/week remote, 4 days/week onsite) We are looking for an experienced Digital SoC Design Verification Principal Engineer/Manager to lead a team of engineers in developing innovative Open RAN SoC functional blocks for 5G cellular base stations. In this role, you will be responsible for driving the development of high-quality digital solutions and contributing to product definition

Mixed-Signal Design Verification EngineerJob Title - Mixed-Signal Design Verification Engineer

Talent Junction, LLC.Company Name - Talent Junction, LLC.

•

San Jose, California, USA

Contract, Third Party

Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key Technical Skills:UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc. Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters

Senior Design Verification Engineer - Ethernet PHY/PCSJob Title - Senior Design Verification Engineer - Ethernet PHY/PCS

SivaltechCompany Name - Sivaltech

•

Santa Clara, California, USA

Contract, Third Party

Job Title: Senior Design Verification Engineer - Ethernet PHY/PCS Location: Santa Clara, CA Job Type: Contract, Full-time Experience: 7+ years We're seeking an experienced Senior Design Verification Engineer with expertise in Ethernet PHY or PCS to join our team in Santa Clara, CA. Responsibilities: - Develop and execute verification plans for Ethernet PHY or PCS - Create and maintain testbenches and test suites - Collaborate with design engineers to resolve verification issues - Strong understa

Senior SOC/ASIC Verification EngineerJob Title - Senior SOC/ASIC Verification Engineer

GAC Solutions Inc.Company Name - GAC Solutions Inc.

•

Phoenix, Arizona, USA

Full-time, Part-time, Contract, Third Party

Role: Senior SOC/ASIC Verification Engineer Location: Arizona - Onsite Contract We're seeking an experienced Design Verification Engineer with 8 10 years of hands-on expertise in SystemVerilog/UVM, EDA tools (Synopsys/Cadence), and scripting (Python, TCL, Perl). Must have experience in functional verification, assertions, and emulation, with a strong track record in ASIC development. Background in verifying GPU/CPU, high-speed interfaces (PCIe, DDR), or data center applications is a plus.

Verification EngineerJob Title - Verification Engineer

Sunrise Systems, Inc.Company Name - Sunrise Systems, Inc.

•

Santa Clara, California, USA

Contract

Job Title: Verification Engineer - Specialized (US) Job ID: 25-08588 Location: Santa Clara, CA 95054 (Hybrid 3 days per week) Duration: 6 Months on W2 contract Job Duties: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team , working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candida

Design Verification EngineerJob Title - Design Verification Engineer

AdientOne LLCCompany Name - AdientOne LLC

•

Massachusetts, USA

Contract

Role: Design Verification Engineer Location: Boxborough MA 01719 | Hybrid Duration: 7 months Job Description: Collaborate with team to verify complex IP blocks. Develop and execute tests. Debug issues related to functionality, performance, and power. Work on functional and/or code coverage closure. Requirements: Proven experience working in UVM and constrained-random simulation environments. Strong knowledge of System Verilog, Verilog, C/C++, and scripting languages. Familiarity with 3D pipelin

Wireless System Verification EngineerJob Title - Wireless System Verification Engineer

Apple, Inc.Company Name - Apple, Inc.

•

No location provided

Full-time

Join Apple's Wireless Verification team and be at the heart of innovation. As a key player in our verification team, you will collaborate closely with multi-functional teams to design and deliver groundbreaking wireless connectivity solutions for current and future Apple products. Experience a multifaceted and intelligent workforce, groundbreaking technologies, and substantial growth opportunities. If you are passionate about wireless technologies, thrive in a fast-paced environment, and are eag

Design Verification EngineerJob Title - Design Verification Engineer

LeadStack, Inc.Company Name - LeadStack, Inc.

•

No location provided

Full-time, Contract

Lead Stack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world. TITLE: Design Verification Engineer LOCATION: San Jose CA/ Austin TX DURATION: 5+ Months with possible extension Rate: $90-$110/hr on W2 Job Descriptio