25 results (4 new)
Remote
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Today
12+ month contractRemote/3 Main priorities below: 1- Tile Based Approach 2-Tessent SSN- specifically SSN 3- MCM Packages/Die-To-Die Chips DFT engineer- Expert with Tessent tools. Experience with Tessent SSN. Experience working on ATPG, MBIST, JTAG, DFT Insertion. Experience with own DFT Verification. Experience with ICL PDL.
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Contract
60 - 90
San Jose, California
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12d ago
Role: Lead ASIC DFT Engineer Location: San Jose, CA (Remote, PST time zone preferred) Work Setup: Remote, PST time zone preferred Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) DFT Architecture definition. Must Full chip / Sub system level DFT activities Must Scan & compression (EDT) implementation Must LBIST implementation and verification any BIST exp is Must Coverage improvements (Spyglass work) Must ATPG Good to Have Role Summar
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Full-time, Third Party, Contract
Depends on Experience
Remote
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Today
Role : Lead ASIC DFT Engineer Location : San Jose, CA (Remote) Duration : 12 Months Job Description: Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon
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Contract
Depends on Experience
Saratoga, California
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2d ago
We re looking for a seasoned DFT Leader to architect and drive test strategy for complex multi-chip SoCs at advanced nodes (7nm and below). Own DFT architecture (Scan, LBIST, MBIST, Memory Repair, OCC, ACJTAG/DCJTAG) Lead ATPG & achieve high @speed scan coverage Hands-on with Synopsys or Mentor test tools Multiple deep submicron tape-outs required SerDes + EMIB exposure is a plus 15+ years semiconductor experience This is a high-impact leadership role shaping next-gen high-performance silicon.
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Full-time
Depends on Experience
Remote
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8d ago
5+ years of SoC-level front-end integration experience Strong background in multi-IP subsystem assembly and third-party IP integrationExperience configuring and integrating NoC / interconnect fabricsGeneral DFT awareness at the SoC integration levelComfortable working cross-functionally with verification, physical design, and DFT teamsProficiency in Verilog / SystemVerilog
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Contract, Third Party
Depends on Experience
San Francisco, California
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Today
Own post-silicon structural test pattern debug and regeneration, including ATPG, MBIST, Boundary Scan, and related DFT flows Analyze pattern failures on silicon and drive corrective actions in collaboration with tester teams Utilize Siemens DFT/ATPG tools to modify, validate, and re-release production-ready test patterns Correlate tester results with design intent to isolate coverage gaps and failure mechanisms Drive closure of post-silicon DFT issues to improve yield and test robustness
Full-time
Hybrid in San Jose, California
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Today
Job Title: Lead ASIC DFT Engineer Location: San Jose, CA - Must Be Able To Go In Office Once Or Twice A Month Duration: Long term Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, bo
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Contract
Depends on Experience
Santa Clara, California
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Today
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin
Full-time
USD 128,000.00 - 189,370.00 per year
Santa Clara, California
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Today
Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you?ll insure it becomes reality. We?re doing a ground up implementation of a new chip architecture, so you?ll have to ability
Full-time
Compensation information provided in the description
Austin, Texas
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Today
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated engineer to work with the Modus Test R&D team working on Design For Test (DFT) and Automatic Test Pattern Generation (ATPG) Software. What You'll Be Doing Work as a team to build reliable, scalable and high performance software that are easy to use by engineers worldwideDevelop software tools in C/C++ to support DFT/ATPGResearch
Full-time
Fort Collins, Colorado
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Today
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our Fort Collins, Colorado, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, thro
Full-time
USD 108,000.00 - 172,800.00 per year
Scottsdale, Arizona
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Today
Basic Qualifications Requires a Bachelor's degree in Electrical Engineering, or a related Science, Engineering or Mathematics field. Also requires one year of experience, or a Master's degree. CLEARANCE REQUIREMENTS:: [Department of Defense Secret security clearance is preferred at time of hire.] Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within
Full-time
USD 85,807.00 - 95,193.00 per year
Morrisville, North Carolina
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Today
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin
Full-time
USD 160,400.00 - 237,320.00 per year
Richardson, Texas
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Today
Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal SoC DFT Engineer within the Heterogeneous Integration Group (HIG), you will be responsible for the DFT architecture, implementation, and signoff of complex HBM base-die System-on-Chi
Full-time
USD 146,000.00 - 309,000.00 per year
Burlington, Vermont
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Today
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin
Full-time
USD 115,200.00 - 170,390.00 per year
San Jose, California
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Today
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is seeking candidates for a Staff DFT engineer position. The successful candidate will be responsible for developing and implementing DFx (Design for Test/debug & manufacturability) solutions for Digital, mixed signal IPs. Candidate will also
Full-time
USD 120,000.00 - 192,000.00 per year
Sunnyvale, California
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Today
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'
Full-time
USD 210,000.00 - 295,000.00 per year
Santa Clara, California
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Today
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo
Full-time
USD 145,600.00 per year
Austin, Texas
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Today
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis. Key Responsibilities: Work closely with the ATE engineer on yield improvement and analy
Full-time
USD 108,000.00 - 192,000.00 per year
Santa Clara, California
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Today
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you'll insure it becomes reality. We're doing a ground up implementation of a new chip architecture, so you'll have to ab
Full-time
USD 142,200.00 - 213,400.00 per year
