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Santa Clara, California

•

Yesterday

Job Title: DFT / ATPG Engineer Location:Santa Clara, CA (Onsite) Duration: 12+ Months Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engineer will work closely with crossfunctional teams to enab

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Contract, Third Party

55 - 60

DFT Engineer

Santa Clara, California

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18d ago

Job Title: DFT Engineer Location: Santa Clara, CA Role Purpose: We are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary Scan Key Responsibilities:Work on Scan insertion, ATPG, GLS (timing/non-timing)Implement MBIST and/or Boundary Scan (BSCAN, JTAG)Support DFT architecture and chip-level integrationDebug DFT issues and improve test coverage Requirements:Experience in at least 2 DFT areas (Scan/ATPG/MBIST/BSCAN/GLS)Strong understanding of DFT concepts and flowExp

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Third Party, Contract

Depends on Experience

DFT Engineer

San Jose, California

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22d ago

Role :- Senior ASIC DFT CDC Constraints Eng Location :- San Jose, CA/Milpitas, CA (Remote) Type :- */W2 This is a highly specialised role at the intersection of Design for Test (DFT) architecture and clock domain crossing (CDC) constraint engineering. The successful candidate will own the SDC/SSTA constraint strategy that governs both functional timing closure and DFT scan-mode operation across a complex multi-clock SoC. You will work daily at the boundary where CDC violations manifest as sca

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Full-time, Third Party

Depends on Experience

Sr DFT Engineer

Santa Clara, California

•

Yesterday

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support client s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engin

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Contract, Third Party

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

Today

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Job Description Key skills for Lead ASIC DFT: please see these key words of in the project description for the profile consideration. SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer

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Full-time, Part-time, Third Party, Contract

Sr. ASIC DFT Engineer (Silicon)

Sunnyvale, California

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4d ago

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 160,000.00 per year

Senior DFT Engineer

Saratoga, California

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4d ago

Ready to make connectivity from space universally accessible, secure and actionable? Then you've come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We're intentional, we're una

Full-time

USD 120,000.00 - 220,000.00 per year

DFT Engineers

Santa Clara, California

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3d ago

Job Title: DFT Engineers Location: Santa Clara, CA Duration: 12 Months Required Skills & Qualifications 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level vali

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Full-time, Third Party

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

Yesterday

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Rate $100/hr C2C Any Visa Job Description 10+ years of hands-on experience in ASIC Design-for-Test (DFT) please see these key words of in the project description for the profile consideration. SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax

Easy Apply

Contract, Third Party

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

16d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation,

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Contract, Third Party

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

4d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Duration - Contract Job Description Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundar

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Contract, Third Party

$75 - $80

Lead ASIC DFT Engineer

Remote

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2d ago

Role: Lead ASIC DFT Engineer Location Remote preferred PST otherwise anywhere in USA Duration: 12+ month contract Job Description Key skills for Lead ASIC DFT: SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutio

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Contract

Depends on Experience

Lead ASIC DFT Engineer

Remote

•

2d ago

Title - Lead ASIC DFT Engineer Location Remote (must be aligned with PST time zone) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of cri

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Third Party, Contract

$70 - $90

DFT Engineer

Remote

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9d ago

3 Main priorities below: 1- Tile Based Approach 2-Tessent SSN- specifically SSN 3- MCM Packages/Die-To-Die Chips DFT engineer- Expert with Tessent tools. Experience with Tessent SSN. Experience working on ATPG, MBIST, JTAG, DFT Insertion. Experience with own DFT Verification. Experience with ICL PDL.

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Contract

Depends on Experience

DFT Engineers - Multiple roles

San Jose, California

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5d ago

Job Detail :- Required Skills & Qualifications 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock verification co

Easy Apply

Full-time

Depends on Experience

DFT Engineer

Remote

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25d ago

Contract role. 12 months Remote 3 Main priorities below: 1- Tile Based Approach 2-TessentSSN- specificallySSN 3- MCM Packages/Die-To-Die ChipsDFT engineer- Expert with Tessent tools. Experience with TessentSSN. Experience working on ATPG, MBIST, JTAG,DFTInsertion. Experience with ownDFTVerification. Experience with ICL PDL.

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Contract, Third Party

60 - 90

Sr DFT Engineer (eInfochips Inc)

Remote or California

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4d ago

Position: Sr DFT Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC levelVerify test patterns using gate-level simulations.Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems.Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. What We Are Looking For: Strong understanding of indust

Full-time

Lead ASIC DFT Engineer

Remote

•

Yesterday

Job Title: Lead ASIC DFT EngineerLocation: Remote (PST time zone)Duration: 12 Months Key skills for Lead ASIC DFT: SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax Experience:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary:We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This

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Third Party, Contract

Depends on Experience

Senior DFT Engineer (Einfochips)

Remote or Arizona

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4d ago

Position: Senior DFT Engineer (Einfochips) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT workRTL checks for scan-insertion compatibility using Synopsys SpyglassScan-Insertion using Tessent TestKompressATPG pattern generation:Compressed and Uncompressed ModeTools: Mentor Tessent, Cadence Modus & Synopsys TetramaxPattern Simulation:Without timing, With timing for different cornersTools: VCSMismatch debug using VerdiScripting with Perl, Shell, T

Full-time

CPU Gate Level Synthesis Engineer

Santa Clara, California

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4d ago

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our p

Full-time

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